In an information processing system having a CPU (Central Processing Unit), direct memory access (DMA) that is data transfer between a resource and a memory or the like not via the CPU is widely adopted. The data transfer by DMA (DMA data transfer) is controlled by a DMA controller (DMAC).
DMA data transfer modes include, for example, a burst transfer mode. The burst transfer mode is a mode in which data transfer for the number of times that is set in advance is executed in response to one transfer request. In the burst transfer mode, after a DMA data transfer operation is started upon the detection of a rising edge (or a falling edge) of a data request signal, the data transfer for the set number of times is executed irrespective of the level that the data request signal has thereafter.
Further, in some DMA data transfer, data transfer takes place during a period when the data request signal has an active level. In this data transfer, the DMA data transfer operation is started when the data request signal becomes active, the data transfer is continued during a period when the data request signal is active, and when the data request signal becomes inactive, the data transfer operation is finished.
Further, Japanese Laid-open Patent Publication No. 06-208540 discloses a DMA controller which, during the execution of the burst transfer, abandons a bus right to release a bus every time it executes the data transfer once, thereby preventing its long-time occupation of the bus. Further, Japanese Laid-open Patent Publication No. 2002-269027 discloses that a rising edge (or a falling edge) of a data request signal is detected to be converted to a one-cycle pulse, the pulse signals are accumulated as request queues, and a DMA controller executes data transfer according to the accumulated Queues.
Here, after starting the DMA data transfer operation, the DMA controller executing the data transfer in the burst transfer mode does not check the level of the data request signal until the data transfer for the set number of transfer times is finished. This makes the DMA controller executing the data transfer in the burst transfer mode incapable of normally executing the data transfer to/from a module that requests the DMA data transfer by using the level of the data request signal. This is because, as illustrated in FIG. 7 as an example, a module requesting the DMA data transfer by using the level of the data request signal may possibly inactivate the data request signal before the data transfer for the number of transfer times set in the DMA controller is finished. Then, when the data request signal becomes inactive before the data transfer for the number of transfer times set in the DMA controller is finished, data transferred thereafter becomes invalid.
In FIG. 7, a data request is the data request signal output from the module and is a signal whose active level is high level (high active). Further, DMA write to the module is data write to the module, and the number of DMAC transfer times is the remaining number of data transfer times in the DMA transfer operation in the burst transfer mode. FIG. 7 illustrates an example where the number of data transfer times set in advance in the DMA controller is six. As illustrated in FIG. 7, when the module requesting the DMA data transfer by using the level of the data request signal inactivates the data request signal at time T71, subsequent writes to the module becomes invalid. Thus, for the module requesting the DMA data transfer by using the level of the data request signal, the burst transfer mode in DMA cannot be used.